Document Outline

COVER
FEATURES
APPLICATIONS
ORDERING INFORMATION
78K/IV SERIES PRODUCT LINEUP
FUNCTIONS
1. DIFFERENCES BETWEEN uPD784908 SUBSERIES PRODUCTS
2. MAJOR DIFFERENCES BETWEEN uPD784908 AND uPD78098 SUBSERIES
3. PIN CONFIGURATION (TOP VIEW)
4. SYSTEM CONFIGURATION EXAMPLE (AUTOMOTIVE CAR AUDIO (TUNER DECK))
5. BLOCK DIAGRAM
6. PIN FUNCTIONS
- 6.1 Port Pins
- 6.2 Non-Port Pins
- 6.3 Pin I/O Circuits and Recommended Connections of Unused Pins
7. CPU ARCHITECTURE
- 7.1 Memory Space
- 7.2 CPU Registers
  - 7.2.1 General-purpose registers
  - 7.2.2 Control registers
  - 7.2.3 Special function registers (SFRs)
8. PERIPHERAL HARDWARE FUNCTIONS
- 8.1 Ports
- 8.2 Clock Generator
- 8.3 Real-Time Output Port
- 8.4 Timers/Counters
- 8.5 Watch Timer
- 8.6 PWM Output (PWM0, PWM1)
- 8.7 A/D Converter
- 8.8 Serial Interface
  - 8.8.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE)
  - 8.8.2 Clocked serial interface (CSI)
- 8.9 Clock Output Function
- 8.10 Edge Detection Function
- 8.11 Watchdog Timer
- 8.12 Simplified IEBus Controller
9. INTERRUPT FUNCTION
- 9.1 Interrupt Source
- 9.2 Vectored Interrupt
- 9.3 Context Switching
- 9.4 Macro Service
- 9.5 Examples of Macro Service Applications
10. LOCAL BUS INTERFACE
- 10.1 Memory Expansion
- 10.2 Memory Space
- 10.3 Programmable Wait
- 10.4 Pseudo-Static RAM Refresh Function
- 10.5 Bus Hold Function
11. STANDBY FUNCTION
12. RESET FUNCTION
13. REGULATOR
14. INSTRUCTION SET
15. ELECTRICAL SPECIFICATIONS
16. PACKAGE DRAWING
17. RECOMMENDED SOLDERING CONDITIONS
APPENDIX A DEVELOPMENT TOOLS
APPENDIX B RELATED DOCUMENTS

1996

DATA SHEET

The mark shows major revised points.

16-BIT SINGLE-CHIP MICROCONTROLLER

MOS INTEGRATED CIRCUIT

PD784907, 784908

Document No. U11680EJ2V0DS00 (2nd edition)
Date Published February 1999 N CP(K)
Printed in Japan

The

PD784907 and

PD784908 are products of the

PD784908 Subseries in the 78K/IV Series. These products

contain various peripheral hardware such as IEBus

controller, ROM, RAM, I/O ports, 8-bit resolution A/D, timers,

serial interface, and interrupt functions, as well as a high-speed, high-performance CPU.

In addition, the

PD78P4908 (one-time PROM product), which is used to evaluate the functions of mask ROM

versions, and development tools are also available.

Detailed function descriptions are provided in the following user's manuals. Be sure to read them before

designing.

PD784908 Subseries User's Manual Hardware : U11787E

78K/IV Series User's Manual Instruction

: U10905E

FEATURES

The information in this document is subject to change without notice.

78K/IV Series

Minimum instruction execution time: 320 ns (at 6.29 MHz)

160 ns (at 12.58 MHz)

Number of I/O ports: 80

Timer/counters: 16-bit timer/counter

3 units

16-bit timer

1 unit

Serial interface: 4 channels

UART/IOE (3-wire serial I/O): 2 channels

CSI (3-wire serial I/O):

2 channels

PWM outputs: 2

Standby function

HALT/STOP/IDLE mode

Clock frequency division function

Watchdog timer: 1 channel

Clock output function

Selectable from f

CLK

, f

CLK

/2, f

CLK

/4, f

CLK

/8, or f

CLK

/16

A/D converter: 8-bit resolution

8 channels

On-chip IEBus controller

Watch timer

Low-power consumption

Supply voltage: V

= 4.0 to 5.5 V

(Main clock: f

= 12.58 MHz,

internal system clock = f

CYK

= 79 ns)

= 3.5 to 5.5 V

(Other than above, f

CYK

= 159 ns)

APPLICATIONS

Car audios, etc.

This document describes the

PD784908 unless otherwise specified.

PD784907, 784908

Data Sheet U11680EJ2V0DS00

78K/IV SERIES PRODUCT LINEUP

PD784026

PD784038Y

C bus supported

PD784038

Enhanced internal memory capacity,
pin compatible with the PD784026

PD784225Y

Multi-master I

C bus supported

PD784225

80 pins,
ROM correction added

PD784218Y

Multi-master I

C bus supported

Multi-master I

C bus supported

PD784218

Enhanced internal memory capacity,
ROM correction added

PD784928Y

Multi-master I

C bus supported

PD784928

Enhanced functions of the PD784915

PD784216Y

PD784054

PD784216

PD784046

PD784908

On-chip 10-bit A/D

100 pins,
enhanced I/O and
internal memory capacity

Enhanced A/D,
16-bit timer,
and power
management

PD784915

For software servo control,
on-chip analog circuit
for VCR,
enhanced timer

On-chip IEBus
controller

Standard models

ASSP models

: Under mass production

: Under development

PD784955

For DC inverter control

PD784938

Enhanced functions of the PD784908,
enhanced internal memory capacity,
ROM correction added

PD784907, 784908

Data Sheet U11680EJ2V0DS00

FUNCTIONS

Part Number

PD784907

PD784908

Item

Number of basic instructions

113

(mnemonics)

General-purpose register

8 bits

16 registers

8 banks, or 16 bits

8 registers

8 banks (memory mapping)

Minimum instruction execution

320 ns/636 ns/1.27

s/2.54

s (at 6.29 MHz)

time

160 ns/320 ns/636 ns/1.27

s (at 12.58 MHz)

Internal

ROM

96 K

128 K

memory

RAM

3,584 bytes

4,352 bytes

Memory space

1 Mbyte with program and data spaces combined

I/O ports

Total

Input

Input/output

Additional

LED direct

function

drive outputs

pins

Note

Transistor

direct drive

N-ch open

drain

Real-time output ports

4 bits

2, or 8 bits

IEBus controller

Incorporated (simplified)

Timer/counter

Timer/counter 0:

Timer register

Pulse output capability

(16 bits)

Capture register

· Toggle output

Compare register

· PWM/PPG output

· One-shot pulse output

Timer/counter 1:

Timer register

Real-time output port

(16 bits)

Capture register

Capture/compare register

Compare register

Timer/counter 2:

Timer register

Pulse output capability

(16 bits)

Capture register

· Toggle output

Capture/compare register

· PWM/PPG output

Compare register

Timer 3:

Timer register

(16 bits)

Compare register

Watch timer

Interrupt requests are generated at 0.5-second intervals. (A watch clock oscillator is

incorporated.)

Either the main clock (6.29 MHz/12.58 MHz) or watch clock (32.7 kHz) can be selected

as the input clock.

Clock output

Selectable from f

CLK

, f

CLK

/2, f

CLK

/4, f

CLK

/8, or f

CLK

/16 (can be used as a 1-bit output port)

PWM outputs

12-bit resolution

2 channels

Serial interface

UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator)

CSI (3-wire serial I/O):

2 channels

A/D converter

8-bit resolution

8 channels

Note Additional function pins are included in the I/O pins.

PD784907, 784908

Data Sheet U11680EJ2V0DS00

CONTENTS

DIFFERENCES BETWEEN

PD784908 SUBSERIES PRODUCTS .......................................

MAJOR DIFFERENCES BETWEEN

PD784908 AND

PD78098 SUBSERIES ..................

PIN CONFIGURATION (TOP VIEW) .........................................................................................

SYSTEM CONFIGURATION EXAMPLE (AUTOMOTIVE CAR AUDIO (TUNER DECK)) .....

BLOCK DIAGRAM .....................................................................................................................

PIN FUNCTION ...........................................................................................................................

6.1

Port Pins ............................................................................................................................................

6.2

Non-Port Pins ...................................................................................................................................

6.3

Pin I/O Circuits and Recommended Connections of Unused Pins ..........................................

CPU ARCHITECTURE ...............................................................................................................

7.1

Memory Space ..................................................................................................................................

7.2

CPU Registers ..................................................................................................................................

7.2.1

General-purpose registers ................................................................................................

7.2.2

Control registers ................................................................................................................

7.2.3

Special function registers (SFRs) ....................................................................................

PERIPHERAL HARDWARE FUNCTIONS ................................................................................

8.1

Ports ...................................................................................................................................................

8.2

Clock Generator ...............................................................................................................................

8.3

Real-Time Output Port .....................................................................................................................

8.4

Timers/Counters ...............................................................................................................................

8.5

Watch Timer ......................................................................................................................................

8.6

PWM Output (PWM0, PWM1) ..........................................................................................................

8.7

A/D Converter ...................................................................................................................................

8.8

Serial Interface .................................................................................................................................

8.8.1

Asynchronous serial interface/3-wire serial I/O (UART/IOE) .......................................

8.8.2

Clocked serial interface (CSI) ...........................................................................................

8.9

Clock Output Function ....................................................................................................................

8.10 Edge Detection Function ................................................................................................................

8.11 Watchdog Timer ...............................................................................................................................

8.12 Simplified IEBus Controller ............................................................................................................

INTERRUPT FUNCTION ............................................................................................................

9.1

Interrupt Source ...............................................................................................................................

9.2

Vectored Interrupt ............................................................................................................................

9.3

Context Switching ............................................................................................................................

9.4

Macro Service ...................................................................................................................................

9.5

Examples of Macro Service Applications ....................................................................................

PD784907, 784908

Data Sheet U11680EJ2V0DS00

10. LOCAL BUS INTERFACE .........................................................................................................

10.1 Memory Expansion ..........................................................................................................................

10.2 Memory Space ..................................................................................................................................

10.3 Programmable Wait .........................................................................................................................

10.4 Pseudo-Static RAM Refresh Function ..........................................................................................

10.5 Bus Hold Function ...........................................................................................................................

11. STANDBY FUNCTION ...............................................................................................................

12. RESET FUNCTION .....................................................................................................................

13. REGULATOR ..............................................................................................................................

14. INSTRUCTION SET ....................................................................................................................

15. ELECTRICAL SPECIFICATIONS ..............................................................................................

16. PACKAGE DRAWING ................................................................................................................

17. RECOMMENDED SOLDERING CONDITIONS ........................................................................

APPENDIX A DEVELOPMENT TOOLS ..........................................................................................

APPENDIX B RELATED DOCUMENTS .........................................................................................

PD784907, 784908

Data Sheet U11680EJ2V0DS00

1. DIFFERENCES BETWEEN

PD784908 SUBSERIES PRODUCTS

The only difference between the

PD784907 and

PD784908 is their internal memory capacities.

The

PD78P4908 is produced by replacing the mask ROM in the

PD784907 or

PD784908 with 128-Kbyte one-

time PROM. Table 1-1 shows the differences between these products.

Table 1-1. Differences between the

PD784908 Subseries Products

Part Number

PD784907

PD784908

PD78P4908

Item

Internal ROM

96 K (mask ROM)

128 K (mask ROM)

128 K (one-time PROM)

Internal RAM

3,584 bytes

4,352 bytes

Regulator

Provided

None

Power supply voltage

= 4.0 to 5.5 V

= 4.5 to 5.5 V

(Main clock: f

= 12.58 MHz, internal system clock = f

(Main clock: f

= 12.58 MHz,

CYK

= 79 ns)

internal system clock = f

= 3.5 to 5.5 V

CYK

= 79 ns)

(other than above, f

CYK

= 159 ns)

= 4.0 to 5.5 V

(other than above,

CYK

= 159 ns)

Electrical specifications

Refer to the data sheet of each product.

PD784907, 784908

Data Sheet U11680EJ2V0DS00

2. MAJOR DIFFERENCES BETWEEN

PD784908 AND

PD78098 SUBSERIES

Series Name

PD784908 Subseries

PD78098 Subseries

Item

Number of basic instructions

113

(mnemonics)

Minimum instruction execution

320/160 ns

480 ns

time

(at 6.29/12.58 MHz operation)

(at 6.29 MHz operation)

Timer/counter

16-bit timer/counter

8/16-bit timer/counter

8/16-bit timer

Watch timer

Single clock

Dual clock

Watch clock for clock operation

Watchdog timer

Provided

Serial interface

UART/IOE (3-wire serial I/O): 2 channels

UART (3-wire serial I/O): 1 channel

CSI (3-wire serial I/O): 2 channels

CSI/SBI (3-wire serial I/O): 1 channel

CSI (3-wire serial I/O): 1 channel

PWM output

None

A/D converter

8-bit resolution

8 channels

D/A converter

None

Interrupt

Hardware source

23 (two test flags)

Internal

External

External extended function

Provided (up to 1 Mbyte)

None

IEBus controller

Incorporated (simplified)

Incorporated (complete hardware)

Power supply voltage

· Mask ROM version

= 2.7 to 6.0 V

= 4.0 to 5.5 V

(Main clock: f

= 12.58 MHz,

internal system clock = f

, f

CYK

= 79 ns)

= 3.5 to 5.5 V

(other than above, f

CYK

= 159 ns)

· PROM version

= 4.5 to 5.5 V

(Main clock: f

= 12.58 MHz,

internal system clock = f

, f

CYK

= 79 ns)

= 4.0 to 5.5 V

(other than above, f

CYK

= 159 ns)

Package

100-pin plastic QFP (14

20 mm)

80-pin plastic QFP (14

14 mm)

80-pin plastic WQFN (14

14 mm):

PD78P098A only

PD784907, 784908

Data Sheet U11680EJ2V0DS00

3. PIN CONFIGURATION (TOP VIEW)

100-pin plastic QFP (14

20 mm)

PD784907GF-

×××

-3BA

PD784908GF-

×××

-3BA

Notes 1. Connect the TEST pin directly to V

2. Connect the REGOFF pin directly to V

(select regulator operation).

3. Connect the REGC pin to V

via a capacitor of the order of 1

P35/TO1

100

P34/TO0

P33/SO0

P32/SCK0

P31/TxD/SO1

P30/RxD/SI1

P27/SI0

P26/INTP5

P25/INTP4/ASCK/SCK1

P24/INTP3

P23/INTP2/CI

P22/INTP1

P21/INTP0

P20/NMI

REF1

P77/ANI7

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

P76/ANI6

P36/TO2

P37/TO3

P100

P101

P102

P103

P104

P105/SCK3

P106/SI3

P107/SO3

RESET

XT2

XT1

REGOFF

Note 2

REGC

Note 3

P00

P01

P02

P03

P04

P05

P06

P07

P67/REFRQ/HLDAK

P66/WAIT/HLDRQ

P65/WR

P75/ANI5

P74/ANI4

P73/ANI3

P72/ANI2

P71/ANI1

P70/ANI0

TEST

Note 1

PWM1

PWM0

P17

P16

P15

P14/TxD2/SO2

P13/RxD2/SI2

P12/ASCK2/SCK2

P11

ASTB/CLKOUT

P10

P90

P91

P92

P93

P94

P95

P96

P97

P40/AD0

P41/AD1

P42/AD2

P64/RD

P63/A19

P62/A18

P61/A17

P60/A16

P57/A15

P56/A14

P55/A13

P54/A12

P53/A11

P52/A10

P51/A9

P50/A8

P47/AD7

P46/AD6

P45/AD5

P44/AD4

P43/AD3

PD784907, 784908

Data Sheet U11680EJ2V0DS00

A8 to A19:

Address bus

AD0 to AD7:

Address/data bus

ANI0 to ANI7:

Analog input

ASCK, ASCK2:

Asynchronous serial clock

ASTB:

Address strobe

Analog power supply

REF1

Reference voltage

Analog ground

CI:

Clock input

CLKOUT:

Clock output

HLDAK:

Hold acknowledge

HLDRQ:

Hold request

INTP0 to INTP5: Interrupt from peripherals

NMI:

Non-maskable interrupt

P00 to P07:

Port 0

P10 to P17:

Port 1

P20 to P27:

Port 2

P30 to P37:

Port 3

P40 to P47:

Port 4

P50 to P57:

Port 5

P60 to P67:

Port 6

P70 to P77:

Port 7

P90 to P97:

Port 9

P100 to P107:

Port 10

PWM0, PWM1:

Pulse width modulation output

RD:

Read strobe

REFRQ:

Refresh request

REGC:

Regulator capacitance

REGOFF:

Regulator off

RESET:

Reset

RX:

IEBus receive data

D, R

D2:

Receive data

SCK0 to SCK3:

Serial clock

SI0 to SI3:

Serial input

SO0 to SO3:

Serial output

TEST:

Test

TO0 to TO3:

Timer output

TX:

IEBus transmit data

D, T

D2:

Transmit data

Power supply

Ground

WAIT:

Wait

WR:

Write strobe

X1, X2:

Crystal (main system clock)

XT1, XT2:

Crystal (watch)

PD784907, 784908

Data Sheet U11680EJ2V0DS00

5. BLOCK DIAGRAM

Remark

The internal ROM and RAM capacities differ depending on the product.

NMI

INTP3

TO0

TO1

INTP0

INTP1

INTP2/CI

TO2

TO3

P00 to P03

P04 to P07

PWM0

PWM1

INTP5

RESET

TEST

X1
X2

REGC

REGOFF

ANI0 to ANI7

TxD/SO1

ASCK/SCK1

RxD/SI1

ASCK2/SCK2

SCK0

SO0

SI0

A8 to A15

P00 to P07

P20 to P27

P10 to P17

P30 to P37

P40 to P47

P50 to P57

P60 to P67

P70 to P77

ASTB /CLKOUT

REFRQ/HLDAK

WAIT/HLDRQ

AD0 to AD7

A16 to A19

REF1

UART/IOE2

Baud-rate
generator

UART/IOE1

Clocked serial
interface

Clock output

Bus interface

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Programmable
interrupt controller

Timer/counter 0

Timer/counter 1

Timer/counter 2

Timer 3

Real-time output
port

PWM

A /D converter

INTP0 to INTP5

(16 bits)

ROM

78K /IV
CPU core

Watchdog timer

Baud-rate
generator

TxD2/SO2

RxD2/SI2

IEBus controller

XT1

XT2

Watch timer

SCK3

SO3

SI3

Clocked serial
interface 3

P90 to P97

P100 to P107

Port 9

Port 10

System control

(regulator)

RAM

PD784907, 784908

Data Sheet U11680EJ2V0DS00

Port 3 (P3):

· 8-bit I/O port.

· Input and output can be specified in 1-bit units.

· The use of on-chip pull-up resistors can be simultaneously specified by

software for all pins in input mode.

· The use of the N-ch open drain can be specified for pins P32 and P33.

6. PIN FUNCTIONS

6.1 Port Pins (1/2)

Pin Name

I/O

Alternate Function

Function

P00 to P07

I/O

Port 0 (P0):

· 8-bit I/O port.

· Can be used as a real-time output port (4 bits

2).

· Input and output can be specified by 1-bit units.

· The use of on-chip pull-up resistors can be simultaneously specified by

software for all pins in input mode.

· Can drive transistors.

P10

I/O

P11

P12

ASCK2/SCK2

P13

RxD2/SI2

P14

TxD2/SO2

P15 to P17

P20

Input

NMI

P21

INTP0

P22

INTP1

P23

INTP2/CI

P24

INTP3

P25

INTP4/ASCK/SCK1

P26

INTP5

P27

SI0

P30

I/O

RxD/SI1

P31

TxD/SO1

P32

SCK0

P33

SO0

P34 to P37

TO0 to TO3

P40 to P47

I/O

AD0 to AD7

Port 4 (P4):

· 8-bit I/O port.

· Input and output can be specified in 1-bit units.

· The use of on-chip pull-up resistors can be simultaneously specified by

software for all pins in input mode.

· Can drive LEDs.

P50 to P57

I/O

A8 to A15

Port 5 (P5):

· 8-bit I/O port.

· Input and output can be specified in 1-bit units.

· The use of on-chip pull-up resistors can be simultaneously specified by

software for all pins in input mode.

· Can drive LEDs.

Port 2 (P2):

· 8-bit input port.

· P20 does not function as a general-purpose port (non-maskable interrupt).

However, the input level can be checked by an interrupt service routine.

· The use of on-chip pull-up resistors can be specified by software for pins

P22 to P27 (in 6-bit units).

· The P25/INTP4/ASCK/SCK1 pin functions as the SCK1 output pin by a

CSIM1 specification.

Port 1 (P1):

· 8-bit I/O port.

· Input and output can be specified in 1-bit units.

· The use of on-chip pull-up resistors can be simultaneously specified by

software for all pins in input mode.

· Can drive LEDs.

PD784907, 784908

Data Sheet U11680EJ2V0DS00

6.1 Port Pins (2/2)

Pin Name

I/O

Alternate Function

Function

P60 to P63

I/O

A16 to A19

P64

P65

P66

WAIT/HLDRQ

P67

REFRQ/HLDAK

P70 to P77

I/O

ANI0 to ANI7

Port 7 (P7):

· 8-bit I/O port.

· Input and output can be specified in 1-bit units.

P90 to P97

I/O

Port 9 (P9):

· 8-bit I/O port.

· Input and output can be specified in 1-bit units.

· The use of on-chip pull-up resistors can be simultaneously specified by

software for all pins in input mode.

P100 to

I/O

P104

P105

SCK3

P106

SI3

P107

SO3

Port 6 (P6):

· 8-bit I/O port.

· Input and output can be specified in 1-bit units.

· The use of on-chip pull-up resistors can be simultaneously specified by

software for all pins in input mode.

Port 10 (P10):

· 8-bit I/O port.

· Input and output can be specified in 1-bit units.

· The use of on-chip pull-up resistors can be simultaneously specified by

software for all pins in input mode.

· The use of the N-ch open drain can be specified for pins P105 and P107.

PD784907, 784908

Data Sheet U11680EJ2V0DS00

6.2 Non-Port Pins (1/2)

Pin Name

I/O

Alternate Function

Function

TO0 to TO3

Output

P34 to P37

Timer output

Input

P23/INTP2

Input of a count clock for timer/counter 2

RxD

Input

P30/SI1

Serial data input (UART0)

RxD2

P13/SI2

Serial data input (UART2)

TxD

Output

P31/SO1

Serial data output (UART0)

TxD2

P14/SO2

Serial data output (UART2)

ASCK

Input

P25/INTP4/SCK1

Baud rate clock input (UART0)

ASCK2

P12/SCK2

Baud rate clock input (UART2)

SI0

Input

P27

Serial data input (3-wire serial I/O 0)

SI1

P30/RxD

Serial data input (3-wire serial I/O 1)

SI2

P13/RxD2

Serial data input (3-wire serial I/O 2)

SI3

P106

Serial data input (3-wire serial I/O 3)

SO0

Output

P33

Serial data output (3-wire serial I/O 0)

SO1

P31/TxD

Serial data output (3-wire serial I/O 1)

SO2

P14/TxD2

Serial data output (3-wire serial I/O 2)

SO3

P107

Serial data output (3-wire serial I/O 3)

SCK0

I/O

P32

Serial clock I/O (3-wire serial I/O 0)

SCK1

P25/INTP4/ASCK

Serial clock I/O (3-wire serial I/O 1)

SCK2

P12/ASCK2

Serial clock I/O (3-wire serial I/O 2)

SCK3

P105

Serial clock I/O (3-wire serial I/O 3)

NMI

Input

P20

External interrupt

INTP0

P21

request

· Input of a count clock for timer/counter 1

· Capture/trigger signal for CR11 or CR12

INTP1

P22

· Input of a count clock for timer/counter 2

· Capture/trigger signal for CR22

INTP2

P23/CI

· Input of a count clock for timer/counter 2

· Capture/trigger signal for CR21

INTP3

P24

· Input of a count clock for timer/counter 0

· Capture/trigger signal for CR02

INTP4

P25/ASCK/SCK1

INTP5

P26

Input of a conversion start trigger for A/D converter

AD0 to AD7

I/O

P40 to P47

Time multiplexing address/data bus (for connecting external memory)

A8 to A15

Output

P50 to P57

High-order address bus (for connecting external memory)

A16 to A19

Output

P60 to P63

High-order address bus during address expansion (for connecting external

memory)

Output

P64

Strobe signal output for reading the contents of external memory

Output

P65

Strobe signal output for writing on external memory

WAIT

Input

P66/HLDRQ

Wait insertion

REFRQ

Output

P67/HLDAK

Refresh pulse output to external pseudo static memory

HLDRQ

Input

P66/WAIT

Input of bus hold request

HLDAK

Output

P67/REFRQ

Output of bus hold response

ASTB

Output

CLKOUT

Latch timing output of time multiplexing address (A0 to A7) (for connecting

external memory)

PD784907, 784908

Data Sheet U11680EJ2V0DS00

6.3 Pin I/O Circuits and Recommended Connections of Unused Pins

The input/output circuit type of each pin and recommended connections of unused pins are shown in Table 6-1.

For each type of input/output circuit, refer to Figure 6-1.

Table 6-1. Types of Pin I/O Circuits and Recommended Connections of Unused Pins (1/2)

Pin Name

I/O Circuit Type

I/O

Recommended Connections of Unused Pins

P00 to P07

5-A

I/O

Input:

Connect to V

P10, P11

Output: Leave open

P12/ASCK2/SCK2

8-A

P13/RxD2/SI2

5-A

P14/TxD2/SO2

P15 to P17

P20/NMI

Input

Connect to V

or V

P21/INTP0

P22/INTP1

2-A

Connect to V

P23/INTP2/CI

P24/INTP3

P25/INTP4/ASCK/SCK1

8-A

I/O

Input:

Connect to V

Output: Leave open

P26/INTP5

2-A

Input

Connect to V

P27/SI0

P30/RxD/SI1

5-A

I/O

Input:

Connect to V

P31/TxD/SO1

Output: Leave open

P32/SCK0

10-A

P33/SO0

P34/TO0 to P37/TO3

5-A

P40/AD0 to P47/AD7

P50/A8 to P57/A15

P60/A16 to P63/A19

P64/RD

P65/WR

P66/WAIT/HLDRQ

P67/REFRQ/HLDAK

P70/ANI0 to P77/ANI7

I/O

Input:

Connect to V

or V

P90 to P97

5-A

Output: Leave open

P100 to P104

P105/SCK3

10-A

P106/SI3

8-A

P107/SO3

10-A

ASTB/CLKOUT

Output

Leave open

PD784907, 784908

Data Sheet U11680EJ2V0DS00

7. CPU ARCHITECTURE

7.1 Memory Space

A memory space of 1 Mbyte can be accessed. By using a LOCATION instruction, the mode for mapping internal

data areas (special function registers and internal RAM) can be selected. A LOCATION instruction must always be

executed after a reset, and can be used only once.

(1) When the LOCATION 0 instruction is executed

· Internal memory

The internal data area and internal ROM area are mapped as follows:

Part Number

Internal Data Area

Internal ROM Area

PD784907

0F100H to 0FFFFH

00000H to 0F0FFH

10000H to 17FFFH

PD784908

0EE00H to 0FFFFH

00000H to 0FDFFH

10000H to 1FFFFH

Caution

The following internal ROM areas, existing at the same addresses as the internal data areas,

cannot be used when the LOCATION 0 instruction is executed:

Part Number

Unusable Area

PD784907

0F100H to 0FFFFH (3,840 bytes)

PD784908

0EE00H to 0FFFFH (4,608 bytes)

· External memory

The external memory is accessed in external memory expansion mode.

(2) When the LOCATION 0FH instruction is executed

· Internal memory

The internal data area and internal ROM area are mapped as follows:

Part Number

Internal Data Area

Internal ROM Area

PD784907

FF100H to FFFFFH

00000H to 17FFFH

PD784908

FEE00H to FFFFFH

00000H to 1FFFFH

· External memory

The external memory is accessed in external memory expansion mode.

PD784907, 784908

Data Sheet U11680EJ2V0DS00

Figure 7-1.

PD784907 Memory Map

Notes 1. Accessed in external memory expansion mode.

2. This 3,840-byte area can be used as an internal ROM area only when the LOCATION 0FH instruction is executed.

3. When the LOCATION 0 instruction is executed:

94,464 bytes

When the LOCATION 0FH instruction is executed: 98,304 bytes

4. Base area and entry area based on a reset or interrupt. However, internal RAM is not used as a reset entry area.

F FF F FH

1 8 0 0 0H
1 7 F F FH

0 FF F FH
0 FFDFH
0 FFD0H
0 FF 0 0H

1 0 0 0 0H

0 FEF FH

0 F 1 0 0H
0 F 0 F FH

0 0 0 0 0H

0 FEF FH

0 FE 8 0H
0 FE 7 FH

0 FE 3 9H

0 FE 0 6H

0 FD0 0H
0 FCF FH

0 F 1 0 0H

1 7 F F F H
1 0 0 0 0 H

0 F 0 F FH

0 1 0 0 0H
0 0 F F FH

0 0 8 0 0H
0 0 7 F FH
0 0 0 8 0H
0 0 0 7 FH

0 0 0 4 0H
0 0 0 3 FH

0 0 0 0 0H

F FEF FH

F FE 8 0H
F FE 7 FH

F FE 3 9H

F FE 0 6H

F FD0 0H
F FCF FH

F F 1 0 0H

F F 1 0 0H
F F 0 F FH

1 8 0 0 0H
1 7 F F FH

0 0 0 0 0H

F FEF FH

F F F D F H
F F F D 0 H
F F F 0 0 H

F F F F F H

1 7 F F FH

When the LOCATION 0
instruction is executed

External memory
(928 Kbytes)

Note 1

Internal ROM
(32,768 bytes)

Special function registers (SFRs)

Note 1

(256 bytes)

Internal RAM
(3,584 bytes)

Internal ROM
(61,696 bytes)

Note 4

General-purpose
registers (128 bytes)

Macro service control

word area (42 bytes)

Data area (512 bytes)

Program/data area
(3,072 bytes)

Program/data area

Note 3

Note 2

CALLF entry area
(2 Kbytes)

CALLT table area
(64 bytes)

Vector table area
(64 bytes)

When the LOCATION 0FH
instruction is executed

Internal RAM
(3,584 bytes)

External memory
(946,432 bytes)

Note 1

Internal ROM

(96 Kbytes)

Note 4

Special function registers (SFRs)

(256 bytes)

Note 1

PD784907, 784908

Data Sheet U11680EJ2V0DS00

Figure 7-2.

PD784908 Memory Map

Notes 1. Accessed in external memory expansion mode.

2. This 4,608-byte area can be used as an internal ROM area only when the LOCATION 0FH instruction is executed.

3. When the LOCATION 0 instruction is executed:

126,464 bytes

When the LOCATION 0FH instruction is executed: 131,072 bytes

4. Base area and entry area based on a reset or interrupt. However, internal RAM is not used as a reset entry area.

FF F F FH

2 0 0 0 0H

0F F F FH

1F F F FH

0F FDFH
0F FD0H
0F F 0 0H
0FEF FH

1 0 0 0 0H

0EE 0 0H
0EDF FH

0 0 0 0 0H

0FEF FH

0FE 8 0H
0FE 7 FH

0FE 3 9H

0FE 0 6H

0FD0 0H
0FCF FH

0EE 0 0H

1 F F F F H
1 0 0 0 0 H

0EDF FH

0 0 8 0 0H
0 0 7 F FH

0 1 0 0 0H
0 0 F F FH

0 0 0 8 0H
0 0 0 7 FH

0 0 0 4 0H
0 0 0 3 FH

0 0 0 0 0H

FFEF FH

FFE 8 0H
FFE 7 FH

FFE 3 9H

FFE 0 6H

FFD0 0H
FFCF FH

FEE 0 0H

FEE 0 0H
FEDF FH

FFEF FH

F F F 0 0 H

F F F D 0 H

F F F D F H

F F F F F H

2 0 0 0 0H
1F F F FH

1F F F FH

0 0 0 0 0H

When the LOCATION 0
instruction is executed

External memory
(896 Kbytes)

Note 1

Internal ROM
(65,536 bytes)

Special function registers (SFRs)

Note 1

(256 bytes)

Internal RAM
(4,352 bytes)

Note 4

Internal ROM

(60,928 bytes)

General-purpose
registers (128 bytes)

Macro service control
word area (42 bytes)

Data area (512 bytes)

Program/data area
(3,840 bytes)

Note 2

Program/data area

Note 3

CALLF entry area
(2 Kbytes)

CALLT table area
(64 bytes)

Vector table area
(64 bytes)

When the LOCATION 0FH
instruction is executed

Special function registers (SFRs)

Note 4

Internal ROM

(128 Kbytes)

External memory
(912,896 bytes)

Note 1

Internal RAM
(4,352 bytes)

Note 1

(256 bytes)

PD784907, 784908

Data Sheet U11680EJ2V0DS00

A (R1)

X (R0)

B (R3)

C (R2)

R11

R10

D (R13)

E (R12)

H (R15)

L (R14)

AX (RP0)

BC (RP1)

RP2

RP3

VP (RP4)

UP (RP5)

DE (RP6)

HL (RP7)

VVP (RG4)

UUP (RG5)

TDE (RG6)

WHL (RG7)

The character strings enclosed in
parentheses represent absolute names.

8 banks

7.2 CPU Registers

7.2.1 General-purpose registers

A set of general-purpose registers consists of sixteen 8-bit general-purpose registers. Two 8-bit general-purpose

registers can be combined to form a 16-bit general-purpose register. Moreover, four 16-bit general-purpose registers,

when combined with an 8-bit register for address extension, can be used as 24-bit address specification registers.

Eight banks of this register set are provided. The user can switch between banks by software or the context switching

function.

General-purpose registers other than the V, U, T, and W registers used for address extension are mapped onto

internal RAM.

Figure 7-3. General-Purpose Register Format

Caution

By setting the RSS bit of PSW to 1, R4, R5, R6, R7, RP2, and RP3 can be used as the X, A, C,

B, AX, and BC registers, respectively. However, this function must be used only when using

programs for the 78K/III series.

PD784907, 784908

Data Sheet U11680EJ2V0DS00

7.2.3 Special function registers (SFRs)

The special function registers are registers with special functions such as mode registers and control registers for

built-in peripheral hardware. The special function registers are mapped onto the 256-byte space between 0FF00H

and 0FFFFH

Note

Note On execution of the LOCATION 0 instruction. FFF00H to FFFFFH when the LOCATION 0FH instruction

is executed.

Caution

Do not access an address in this area where no SFR is allocated, as the

PD784908 may be placed

in the deadlock state. The deadlock state can be cleared only by a reset.

Table 7-1 lists the special function registers (SFRs). The symbols of the table columns are explained below.

· Symbol .................................... Symbol indicating an on-chip SFR. The symbols listed in the table are reserved

words for the NEC assembler (RA78K4). In the C compiler (CC78K4), the

symbols can be used as sfr variables with the #pragma sfr command.

· R/W ......................................... Indicates whether the SFR is read-only, write-only, or read/write.

R/W: Read/write

Read-only.

Write-only.

· Bit units for manipulation ....... Indicates the maximum number of bits that can be manipulated whenever an SFR

is manipulated. An SFR that supports 16-bit manipulation can be described in

the sfrp operand. For address specification, an even-numbered address must

be specified.

An SFR that can be manipulated in 1-bit units can be described as the operand

of a bit manipulation instruction.

· After reset ............................... Indicates the state of the register when the RESET signal has been input.

PD784907, 784908

Data Sheet U11680EJ2V0DS00

Table 7-1. Special Function Registers (SFRs) (1/5)

Address

Note

Special Function Register (SFR) Name

Symbol

R/W Bit Units for Manipulation

After Reset

1 bit

8 bits 16 bits

0FF00H

Port 0

R/W

Undefined

0FF01H

Port 1

0FF02H

Port 2

0FF03H

Port 3

R/W

0FF04H

Port 4

0FF05H

Port 5

0FF06H

Port 6

00H

0FF07H

Port 7

Undefined

0FF09H

Port 9

0FF0AH

Port 10

P10

0FF0EH

Port 0 buffer register L P0L

0FF0FH

Port 0 buffer register H

P0H

0FF10H

Compare register (timer/counter 0)

CR00

0FF12H

Capture/compare register (timer/counter 0)

CR01

0FF14H

Compare register L (timer/counter 1)

CR10 CR10W

0FF15H

Compare register H (timer/counter 1)

0FF16H

Capture/compare register L (timer/counter 1)

CR11 CR11W

0FF17H

Capture/compare register H (timer/counter 1)

0FF18H

Compare register L (timer/counter 2)

CR20 CR20W

0FF19H

Compare register H (timer/counter 2)

0FF1AH

Capture/compare register L (timer/counter 2)

CR21 CR21W

0FF1BH

Capture/compare register H (timer/counter 2)

0FF1CH

Compare register L (timer 3)

CR30 CR30W

0FF1DH

Compare register H (timer 3)

0FF20H

Port 0 mode register

PM0

FFH

0FF21H

Port 1 mode register

PM1

0FF23H

Port 3 mode register

PM3

0FF24H

Port 4 mode register

PM4

0FF25H

Port 5 mode register

PM5

0FF26H

Port 6 mode register

PM6

0FF27H

Port 7 mode register

PM7

0FF29H

Port 9 mode register

PM9

0FF2AH

Port 10 mode register

PM10

0FF2EH

Real-time output port control register

RTPC

00H

0FF30H

Capture/compare control register 0

CRC0

10H

0FF31H

Timer output control register

TOC

00H

0FF32H

Capture/compare control register 1

CRC1

0FF33H

Capture/compare control register 2

CRC2

10H

Note When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, F0000H

is added to each address.

PD784907, 784908

Data Sheet U11680EJ2V0DS00

Address

Note

Special Function Register (SFR) Name

Symbol

R/W Bit Units for Manipulation

After Reset

1 bit

8 bits 16 bits

0FF36H

Capture register (timer/counter 0)

CR02

0000H

0FF38H

Capture register L (timer/counter 1)

CR12 CR12W

0FF39H

Capture register H (timer/counter 1)

0FF3AH

Capture register L (timer/counter 2)

CR22 CR22W

0FF3BH

Capture register H (timer/counter 2)

0FF41H

Port 1 mode control register

PMC1

R/W

00H

0FF43H

Port 3 mode control register

PMC3

0FF4AH

Port 10 mode control register

PMC10

0FF4EH

PUOL

0FF4FH

PUOH

0FF50H

Timer register 0

TM0

0000H

0FF51H

0FF52H

Timer register 1

TM1

TM1W

0FF53H

0FF54H

Timer register 2

TM2

TM2W

0FF55H

0FF56H

Timer register 3

TM3

TM3W

0FF57H

0FF5CH

Prescaler mode register 0

PRM0

R/W

11H

0FF5DH

Timer control register 0

TMC0

00H

0FF5EH

Prescaler mode register 1

PRM1

11H

0FF5FH

Timer control register 1

TMC1

00H

0FF68H

A/D converter mode register

ADM

00H

0FF6AH

A/D conversion result register

ADCR

Undefined

0FF6CH

A/D current cut selection register

IEAD

R/W

00H

0FF6FH

Clock timer mode register

0FF70H

PWM control register

PWMC

05H

0FF71H

PWM prescaler register

PWPR

00H

0FF72H

PWM modulo register 0

PWM0

Undefined

0FF74H

PWM modulo register 1

PWM1

0FF7DH

One-shot pulse output control register

OSPC

00H

0FF80H

Clocked serial interface mode register 3

CSIM3

0FF82H

Clocked serial interface mode register

CSIM

Table 7-1. Special Function Registers (SFRs) (2/5)

Note When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, F0000H

is added to each address.

PD784907, 784908

Data Sheet U11680EJ2V0DS00

Address

Note

Special Function Register (SFR) Name

Symbol

R/W Bit Units for Manipulation

After Reset

1 bit

8 bits 16 bits

0FF84H

Clocked serial interface mode register 1

CSIM1

R/W

00H

0FF85H

Clocked serial interface mode register 2

CSIM2

0FF86H

Serial shift register

SIO

Undefined

0FF88H

Asynchronous serial interface mode register

ASIM

00H

0FF89H

Asynchronous serial interface mode register 2

ASIM2

0FF8AH

Asynchronous serial interface status register

ASIS

0FF8BH

Asynchronous serial interface status register 2

ASIS2

0FF8CH

Serial receive buffer: UART0

RXB

Undefined

Serial transmission shift register: UART0

TXS

Serial shift register: IOE1

SIO1

R/W

0FF8DH

Serial receive buffer: UART2

RXB2

Serial transmission shift register: UART2

TXS2

Serial shift register: IOE2

SIO2

R/W

0FF8EH

Serial shift register 3: IOE3

SIO3

0FF90H

Baud rate generator control register

BRGC

00H

0FF91H

Baud rate generator control register 2

BRGC2

0FFA0H

External interrupt mode register 0

INTM0

0FFA1H

External interrupt mode register 1

INTM1

0FFA4H

Sampling clock selection register

SCS0

0FFA8H

In-service priority register

ISPR

0FFAAH

Interrupt mode control register

IMC

R/W

80H

0FFACH

Interrupt mask register 0L

MK0L MK0

FFFFH

0FFADH

Interrupt mask register 0H

MK0H

0FFAEH

Interrupt mask register 1L

MK1L MK1

FFFFH

0FFAFH

Interrupt mask register 1H

MK1H

0FFB0H

Bus control register

BCR

00H

0FFB2H

Unit address register

UAR

0000H

0FFB4H

Slave address register

SAR

0FFB6H

Partner address register

PAR

0FFB8H

Control data register

CDR

R/W

01H

0FFB9H

Telegraph length register

DLR

Table 7-1. Special Function Registers (SFRs) (3/5)

Note Applicable when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed,

F0000H is added to each address.

PD784907, 784908

Data Sheet U11680EJ2V0DS00

Address

Note

Special Function Register (SFR) Name

Symbol

R/W Bit Units for Manipulation

After Reset

1 bit

8 bits 16 bits

0FFBAH

Data register

R/W

00H

0FFBBH

Unit status register

USR

0FFBCH

Interrupt status register

ISR

R/W

0FFBDH

Slave status register

SSR

41H

0FFBEH

Success count register

SCR

01H

0FFBFH

Communication count register

CCR

20H

0FFC0H

Standby control register

STBC

R/W

Note 2

30H

0FFC2H

Watchdog timer mode register

WDM

Note 2

00H

0FFC4H

Memory expansion mode register

20H

0FFC5H

Hold mode register

HLDM

00H

0FFC6H

Clock output mode register

CLOM

0FFC7H

Programmable wait control register 1

PWC1

AAH

0FFC8H

Programmable wait control register 2

PWC2

AAAAH

0FFCCH

Refresh mode register

RFM

00H

0FFCDH

Refresh area specification register

RFA

0FFCFH

Oscillation stabilization time specification register OSTS

0FFD0H to

External SFR area

0FFDFH

0FFE0H

Interrupt control register (INTP0)

PIC0

43H

0FFE1H

Interrupt control register (INTP1)

PIC1

0FFE2H

Interrupt control register (INTP2)

PIC2

0FFE3H

Interrupt control register (INTP3)

PIC3

0FFE4H

Interrupt control register (INTC00)

CIC00

0FFE5H

Interrupt control register (INTC01)

CIC01

0FFE6H

Interrupt control register (INTC10)

CIC10

0FFE7H

Interrupt control register (INTC11)

CIC11

0FFE8H

Interrupt control register (INTC20)

CIC20

0FFE9H

Interrupt control register (INTC21)

CIC21

0FFEAH

Interrupt control register (INTC30)

CIC30

0FFEBH

Interrupt control register (INTP4)

PIC4

0FFECH

Interrupt control register (INTP5)

PIC5

0FFEDH

Interrupt control register (INTAD)

ADIC

0FFEEH

Interrupt control register (INTSER)

SERIC

Table 7-1. Special Function Registers (SFRs) (4/5)

Notes 1. When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed,

F0000H is added to each address.

2. A write operation can be performed only with special instructions MOV STBC,#byte and MOV

WDM,#byte. Other instructions cannot perform a write operation.

PD784907, 784908

Data Sheet U11680EJ2V0DS00

Address

Note

Special Function Register (SFR) Name

Symbol

R/W Bit Units for Manipulation

After Reset

1 bit

8 bits 16 bits

0FFEFH

Interrupt control register (INTSR)

SRIC

R/W

43H

Interrupt control register (INTCSI1)

CSIIC1

0FFF0H

Interrupt control register (INTST)

STIC

0FFF1H

Interrupt control register (INTCSI)

CSIIC

0FFF2H

Interrupt control register (INTSER2)

SERIC2

0FFF3H

Interrupt control register (INTSR2)

SRIC2

Interrupt control register (INTCSI2)

CSIIC2

0FFF4H

Interrupt control register (INTST2)

STIC2

0FFF6H

Interrupt control register (INTIE1)

IEIC1

0FFF7H

Interrupt control register (INTIE2)

IEIC2

0FFF8H

Interrupt control register (INTW)

WIC

0FFF9H

Interrupt control register (INTCSI3)

CSIIC3

0FFFCH

Internal memory size switching register

Note 2

IMS

FFH

Table 7-1. Special Function Registers (SFRs) (5/5)

Notes 1. When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed,

F0000H is added to each address.

2. A write to this register is meaningful only for the

PD78P4908.

PD784907, 784908

Data Sheet U11680EJ2V0DS00

Table 8-1. Port Functions

Port Name

Pin Name

Function

Specification of Pull-up Resistor Connection by Software

Port 0

P00 to P07

· Input or output mode can be specified

All port pins in input mode

in 1-bit units

· Operable as 4-bit real-time outputs

(P00 to P03, P04 to P07)

· Can drive transistors

Port 1

P10 to P17

· Input or output mode can be specified

All port pins in input mode

in 1-bit units

· Can drive LEDs

Port 2

P20 to P27

· Input port

In 6-bit units (P22 through P27)

Port 3

P30 to P37

· Input or output mode can be specified

All port pins in input mode

in 1-bit units

· Either pin P32/SCK0 or P33/SO0 can be

set as the N-ch open drain.

Port 4

P40 to P47

· Input or output mode can be specified

All port pins in input mode

in 1-bit units

· Can drive LEDs

Port 5

P50 to P57

· Input or output mode can be specified

All port pins in input mode

in 1-bit units

· Can drive LEDs

Port 6

P60 to P67

· Input or output mode can be specified

All port pins in input mode

in 1-bit units

Port 7

P70 to P77

· Input or output mode can be specified

in 1-bit units

Port 9

P90 to P97

· Input or output mode can be specified

All port pins in input mode

in 1-bit units

Port 10

P100 to P107 · Input or output mode can be specified

All port pins in input mode

in 1-bit units

· Either pin P105/SCK3 or P107/SO3 can

be set as the N-ch open drain.

PD784907, 784908

Data Sheet U11680EJ2V0DS00

Timer register 3

(TM3/TM3W)

Compare register

(CR30/CR30W)

Prescaler

UART, CSI

Clear

Match

INTC30

Figure 8-6. Timer/Counter Block Diagram

Timer/counter 0

Timer/counter 1

Timer/counter 2

Timer 3

Remark

OVF: Overflow flag

TO1

OVF

TO0

INTP3

INTC00

INTC01

Clear control

Prescaler

Selector

Timer register 0

(TM0)

Software trigger

Compare register

(CR00)

Match

Pulse output control

Compare register

(CR01)

Edge
detection

Capture register

(CR02)

OVF

INTP0

INTC10

INTC11

Clear control

Prescaler

Selector

Timer register 1

(TM1/TM1W)

Event input

Compare register

(CR10/CR10W)

Match

Edge
detection

Capture/compare register

(CR11/CR11W)

To real-time
output port

Capture register

(CR12/CR12W)

TO3

OVF

TO2

INTP1

INTC20

INTC21

INTP2/CI

INTP2

Clear control

Prescaler

Selector

Timer register 2

(TM2/TM2W)

Edge
detection

Compare register

(CR20/CR20W)

Match

Capture/compare register

(CR21/CR21W)

Pulse output control

Capture register

(CR22/CR22W)

PD784907, 784908

Data Sheet U11680EJ2V0DS00

8.5 Watch Timer

As the count clock, either of two types of clock can be input to the watch timer: the main clock (6.29 MHz/12.58

MHz) or the watch clock (32.768 kHz). They can be selected using the control register. The watch clock is input to

the watch timer only. It is not input to the CPU or other peripheral circuits. Therefore, the speed of CPU operation

cannot be slowed by the watch clock.

The watch timer generates interrupt signals (INTW), at 0.5-second intervals

Note

, by dividing the count clock. At

the same time, the watch timer sets the interrupt request flag (WIF) (where WIF refers to bit 7 of the interrupt control

By switching modes, the INTW generation interval can be changed to about 1 ms (fast-forward mode: normal

operation speed

512).

When the main clock is selected as the count clock, the watch timer stops if in STOP or IDLE standby mode, but

continues operating if in HALT standby mode. When the watch clock is selected as the count clock, the watch timer

continues operating regardless of the standby mode. The operation of the watch clock oscillator is controlled by means

of the watch timer mode register (WM).

The watch timer of the

PD784908 does not have a buzzer output function.

Note After the operation is enabled, the time until first INTW generation is not 0.5 s.

Table 8-3. Relationship between Count Clock and Watch Timer Operation

Count Clock Selection

Normal Operation Mode

Standby Modes

HALT mode

STOP mode

IDLE mode

Main clock

Operable

Stopped

Watch clock

Operable

The watch timer consists of a frequency divider which divides the count clock by 3 and a counter which divides

the frequency output from the frequency divider by 2

. As the count clock, select the signal obtained by dividing the

internal system clock by 128 or that output by the watch clock oscillator.

Figure 8-7. Watch Timer Block Diagram

ON/OFF

WM.7

WM.6

SEL

1 2

3 4 5

6 7 8 9

10 11 12 13

WM.2

INTW

STBC.7

WM.3
Reset

Main clock

/128

Division
by 3

Counter

Watch
clock
oscillator

Main clock selection: 6.29 MHz
12.58 MHz

PD784907, 784908

Data Sheet U11680EJ2V0DS00

8.7 A/D Converter

An analog/digital (A/D) converter having 8 multiplexed analog inputs (ANI0 through ANI7) is incorporated.

The successive approximation system is used for conversion. The result of conversion is held in the 8-bit A/D

conversion result register (ADCR). Thus, speedy high-precision conversion can be achieved.

A/D conversion can be started in the following two ways:

· Hardware start: Conversion is started by trigger input (INTP5).

· Software start: Conversion is started by setting the bit of the A/D converter mode register (ADM).

After conversion has started, one of the following modes can be selected:

· Scan mode: Multiple analog inputs are selected sequentially to convert multiple pins.

· Select mode: A single analog input is selected at all times to enable conversion data to be obtained continuously.

ADM is used to specify the above modes, as well as the termination of conversion.

When the result of conversion is transferred to ADCR, an interrupt request (INTAD) is generated. Using this feature,

the results of conversion can be continuously transferred to memory by the macro service.

Cautions

1. For this product, apply the same voltage as the power supply voltage (AV

) to the reference

voltage input pin (AV

REF1

2. When port 7 is used as both an output port and A/D input line, do not manipulate the output

port while A/D conversion is in progress.

Figure 8-9. Block Diagram of A/D Converter

ANI0

ANI7

INTP5

REF1

R/2

Input selector

Tap selector

Sample and hold circuit

Voltage comparator

Successive

approximation

Connection
control

A/D current cut selection
register (IEAD)

Series resistor string

Control
circuit

A/ D converter mode
register (ADM)

A/ D conversion
result register (ADCR)

Internal bus

Edge
detection
circuit

Conversion
trigger

Trigger enable

INTAD

ANI1
ANI2
ANI3
ANI4
ANI5
ANI6

PD784907, 784908

Data Sheet U11680EJ2V0DS00

RXB, RXB2

TXS, TXS2

INTST, INTST2

INTSR,
INTSR2
INTSER,
INTSER2

1/2m

ASCK, ASCK2

TxD, TxD2

RxD, RxD2

1/2

n+1

1/2m

Baud rate generator

Receive
shift register

Receive buffer

Selector

Transmission
control parity
bit addition

Transmission
shift register

Internal bus

Reception
control parity
check

8.8.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE)

Two serial interface channels, from which asynchronous serial interface mode and 3-wire serial I/O mode can be

selected, are provided.

(1) Asynchronous serial interface mode

In this mode, 1-byte data is transferred or received after a start bit.

A baud rate generator is incorporated to enable communication at a wide range of baud rates.

A baud rate can be defined by dividing the frequency of a clock signal input to the ASCK pin.

By using the baud rate generator, a baud rate conforming to the MIDI standard (31.25 kbps) can be obtained.

Figure 8-11. Block Diagram of Asynchronous Serial Interface Mode

Remark

: Oscillating frequency or external clock input frequency

n = 0 to 11

m = 16 to 30

PD784907, 784908

Data Sheet U11680EJ2V0DS00

8.10 Edge Detection Function

The interrupt input pins (NMI, INTP0 through INTP5) are used not only to input interrupt requests but also to input

trigger signals to the internal hardware units. Because these pins operate at the edge of the input signal, they have

an edge-detection function incorporated. Moreover, a noise elimination function is also provided to prevent erroneous

edge detection caused by noise.

Table 8-4. Noise Elimination Method of Interrupt Input Pins

Pin Name

Detectable Edge

Noise Elimination Method

NMI

Rising edge or falling edge

Analog delay

INTP0 to INTP3

Rising edge or falling edge, or both edges

Clock sampling

Note

INTP4, INTP5

Analog delay

Note INTP0 is used for sampling clock selection.

8.11 Watchdog Timer

A watchdog timer is incorporated to detect a CPU runaway. The watchdog timer, if not cleared by software within

a specified interval, generates a non-maskable interrupt request. Furthermore, once watchdog timer operation is

enabled, it cannot be disabled by software. The user can specify whether priority is placed on an interrupt request

based on the watchdog timer or on an interrupt request based on the NMI pin.

Figure 8-15. Block Diagram of Watchdog Timer

CLK

INTWDT

CLK

Timer

Clear signal

Selector

PD784907, 784908

Data Sheet U11680EJ2V0DS00

8.12 Simplified IEBus Controller

A newly developed IEBus controller is incorporated into the

PD784908. This IEBus controller has fewer functions

than the IEBus interface function of previous product (incorporated into the 78K/0).

Table 8-5 compares the previous product and the new, simplified IEBus interface.

Table 8-5. Comparisons between Previous Product and Simplified IEBus Interface

Item

Previous Product (IEBus Incorporated into 78K/0)

Simplified IEBus

Communication mode

Modes 0 to 2

Fixed to mode 1

Internal system clock

6.0 (6.29) MHz

Internal buffer size

Transmission buffer 33 bytes (FIFO)

Transmission/reception data register 1 byte

Reception buffer 40 bytes (FIFO)

Up to four frames can be received

CPU processing

Processing before transmission start (data setting)

Setting and control of each communication status

Data write to the transmission buffer

Data write processing for every byte

Data read from the reception buffer

Data read processing for every byte

Transmission control such as slave status

Control of multiple frames, remastering request

Hardware processing

Bit processing

(modulation/demodulation, error detection)

Field processing (generation, control)

Detection of arbitration results

Parity processing (generation, error detection)

ACK/NACK automatic response

Automatic data retransmitting

Automatic remastering

Transmission such as automatic slave status

Reception of multiple frames

PD784907, 784908

Data Sheet U11680EJ2V0DS00

· Hardware configuration and functions

The internal configuration of the IEBus consists mainly of the following six sections:

· CPU interface section

· Interrupt control section

· Internal register section

· Bit processing section

· Field processing section

· IEBus interface section

<CPU interface section>

Interfaces between the CPU (78K/IV) and the IEBus.

<Interrupt control section>

Passes interrupt request signals from the IEBus to the CPU.

<Internal register section>

Control register which stores the data in each field to control the IEBus.

<Bit processing section>

Generates and resolves the bit timing. Mainly consists of the bit sequence ROM, 8-bit preset timer, and

discriminator.

<Field processing section>

Generates each field in the communication frame. Mainly consists of the field sequence ROM, 4-bit down counter,

and discriminator.

<IEBus interface section>

Interface section of the external driver/receiver. Mainly consists of the noise filter, shift register, conflict detector,

parity detector, parity generator, and ACK/NACK generator.

PD784907, 784908

Data Sheet U11680EJ2V0DS00

9. INTERRUPT FUNCTION

The three types of interrupt request-response servicing, as shown in Table 9-1 below, can be selected by program.

Table 9-1. Servicing of Interrupt Request

Servicing Mode

Servicing Agent

Servicing

PC and PSW Contents

Vectored interrupt

Software

Branches and executes a servicing routine

Saves to and restores from the stack.

(servicing is arbitrary).

Context switching

Automatically switches register banks, and

Saves to or restores from fixed area in

branches and executes a servicing routine

the register bank.

(servicing is arbitrary).

Macro service

Firmware

Executes data transfer between memory and

Maintained

I/O (servicing is fixed).

9.1 Interrupt Source

Table 9-2 shows the interrupt sources available. As shown, interrupts are generated by 27 types of sources,

execution of the BRK and BRKCS instructions, or an operand error.

Four levels of interrupt servicing priority can be set. Priority levels can be set to nest control during interrupt servicing

or to simultaneously generate interrupt requests. However, nested macro services are performed without suspension.

When interrupt requests having the same priority level are generated, they are serviced according to the default

priority (fixed) (see Table 9-2).

PD784907, 784908

Data Sheet U11680EJ2V0DS00

Table 9-2. Interrupt Source

Type

Default

Source

Internal/

Macro

Priority

Name

Trigger

External Service

Software

BRK instruction

Instruction execution

BRKCS instruction Instruction execution

Operand error

When the MOV STBC,#byte, MOV WDM,#byte, or LOCATION

instruction is executed, exclusive OR of the byte operand and

byte does not produce FFH.

Non-maskable

NMI

Detection of edge input on the pin

External

WDT

Watchdog timer overflow

Internal

Maskable

0 (highest) INTP0

Detection of edge input on the pin (TM1/TM1W capture trigger) External

INTP1

Detection of edge input on the pin (TM2/TM2W capture trigger)

INTP2

Detection of edge input on the pin (TM2/TM2W event counter

input)

INTP3

Detection of edge input on the pin (TM0 capture trigger)

INTC00

TM0-CR00 match signal issued

Internal

INTC01

TM0-CR01 match signal issued

INTC10

TM1-CR10 match signal issued (in 8-bit operation mode)

TM1W-CR10W match signal issued (in 16-bit operation mode)

INTC11

TM1-CR11 match signal issued (in 8-bit operation mode)

TM1W-CR11W match signal issued (in 16-bit operation mode)

INTC20

TM2-CR20 match signal issued (in 8-bit operation mode)

TM2W-CR20W match signal issued (in 16-bit operation mode)

INTC21

TM2-CR21 match signal issued (in 8-bit operation mode)

TM2W-CR21W match signal issued (in 16-bit operation mode)

INTC30

TM3-CR30 match signal issued (in 8-bit operation mode)

TM3W-CR30W match signal issued (in 16-bit operation mode)

INTP4

Detection of edge input on the pin

External

INTP5

Detection of edge input on the pin

(A/D converter start conversion trigger)

INTAD

A/D converter processing completed (ADCR transfer)

Internal

INTSER

ASI0 reception error

INTSR

ASI0 reception completed or CSI1 transfer completed

INTCSI1

INTST

ASI0 transmission completed

INTCSI

CSI0 transfer completed

INTSER2

ASI2 reception error

INTSR2

ASI2 reception completed or CSI2 transfer completed

INTCSI2

INTST2

ASI2 transmission completed

INTIE1

IEBus data access request

INTIE2

IEBus communication error and communication start/end

INTW

Clock timer output

24 (lowest) INTCSI3

CSI3 transfer completed

Remark

ASI: Asynchronous serial interface

CSI: Clocked serial interface

PD784907, 784908

Data Sheet U11680EJ2V0DS00

Interrupt Source

Vector Table Address

BRK instruction

003EH

Operand error

003CH

NMI

0002H

WDT

0004H

INTP0

0006H

INTP1

0008H

INTP2

000AH

INTP3

000CH

INTC00

000EH

INTC01

0010H

INTC10

0012H

INTC11

0014H

INTC20

0016H

INTC21

0018H

INTC30

001AH

INTP4

001CH

INTP5

001EH

INTAD

0020H

INTSER

0022H

INTSR

0024H

INTCSI1

INTST

0026H

INTCSI

0028H

INTSER2

002AH

INTSR2

002CH

INTCSI2

INTST2

002EH

9.2 Vectored Interrupt

When a branch to an interrupt servicing routine occurs, the vector table address corresponding to the interrupt

source is used as the branch address.

Interrupt servicing by the CPU consists of the following operations :

· When branching: Saves the CPU status (PC and PSW contents) to the stack.

· When returning:

Restores the CPU status (PC and PSW contents) from the stack.

To return control from the servicing routine to the main routine, the RETI instruction is used.

The branch destination addresses must be within the range of 0 to FFFFH.

Table 9-3. Vector Table Address

Interrupt Source

Vector Table Address

NTIE1

0032H

INTIE2

0034H

INTW

0036H

INTCSI3

0038H

PD784907, 784908

Data Sheet U11680EJ2V0DS00

CPU

SFR

Memory

Read

Write

Read

Write

Macro service
controller

Internal bus

9.3 Context Switching

When an interrupt request is generated, or when the BRKCS instruction is executed, a predetermined register bank

is selected by the hardware. Then, a branch to a vector address stored in that register bank occurs. At the same

time, the contents of the current program counter (PC) and program status word (PSW) are stacked in the register

bank.

The branch address must be within the range of 0 to FFFFH.

Figure 9-1. Context Switching Operation When Interrupt Request Is Generated

9.4 Macro Service

The macro service function enables data transfer between memory and special function registers (SFRs) without

requiring the intervention of the CPU. The macro service controller accesses both memory and SFRs within the same

transfer cycle to directly transfer data without having to perform data fetch.

Since the CPU status is neither saved nor restored, nor is data fetch performed, high-speed data transfer is possible.

Figure 9-2. Macro Service

PSW

PC19-16

0000B

PC15-0

Exchange

Save

<2>

<3>

<4>

<5>

Save

<1>

<6>

<7>

Transfer

(Bits 8 to 11 of
temporary register)

Temporary register

Switching between register banks

(RBS0-RBS2

RSS

PD784907, 784908

Data Sheet U11680EJ2V0DS00

(3) Real-time output port

INTC10 and INTC11 function as the output triggers for the real-time output ports. For these triggers, the macro

service can simultaneously set the next output pattern and interval. Therefore, INTC10 and INTC11 can be used

to independently control two stepping motors. They can also be applied to PWM and DC motor control.

Each time macro service request (INTC10) is generated, a pattern and timing data are transferred to the buffer

match, another INTC10 is generated, and the P0L contents are transferred to the output latch. When Tn (last

byte) is transferred to CR10, vectored interrupt request (INTC10) is generated.

For INTC11, the same operation as that performed for INTC10 is performed.

Match

(SFR)

INTC10

P00 to P03

(SFR)

Output pattern profile (memory)

Output timing profile (memory)

Internal bus

P0L

Output latch

CR10

TM1

Internal bus

PD784907, 784908

Data Sheet U11680EJ2V0DS00

10.3 Programmable Wait

When the memory space is divided into eight spaces, a wait state can be separately inserted for each memory space

while the RD or WR signal is active. This prevents the overall system efficiency from being degraded even when

memory devices having different access times are connected.

In addition, an address wait function that extends the ASTB signal active period is provided to ensure the lapse

of the address decode time. (This function is set for the entire space.)

10.4 Pseudo-Static RAM Refresh Function

Refresh is performed as follows:

· Pulse refresh

A bus cycle is inserted where a refresh pulse is output on the REFRQ pin at regular intervals. When the memory

space is divided into eight, and a specified area is being accessed, refresh pulses can also be output on the

REFRQ pin as the memory is being accessed. This can prevent the refresh cycle from suspending normal

memory access.

· Power-down self-refresh

In standby mode, a low-level signal is output on the REFRQ pin to maintain the contents of pseudo-static RAM.

10.5 Bus Hold Function

A bus hold function is provided to facilitate connection to devices such as a DMA controller. When a bus hold request

signal (HLDRQ) is received from an external bus master, the address bus, address/data bus, and ASTB, RD, and

WR pins enter the high-impedance state, the bus hold acknowledge signal (HLDAK) is made active, and the bus is

released to the external bus master as soon as the current bus cycle is completed.

While the bus hold function is being used, the external wait and pseudo-static RAM refresh functions are disabled.

PD784907, 784908

Data Sheet U11680EJ2V0DS00

11. STANDBY FUNCTION

This function is to reduce the power consumption of the chip, and can be used in the following modes:

· HALT mode: Stops the operating clock of the CPU. This mode is used in combination with the normal operation

mode for intermittent operation to reduce the average power consumption.

· IDLE mode: Stops the entire system with the oscillator continuing operation. The power consumption in this

mode is close to that in the STOP mode. However, the time required to restore the normal program

operation from this mode is almost the same as that from the HALT mode.

· STOP mode: Stops the oscillator and thereby stops all the internal operations of the chip. Consequently, the

power consumption is minimized with only leakage current flowing.

These modes are programmable.

The macro service can be started from the HALT mode.

Figure 11-1. Standby Mode Status Transition

Notes 1. INTW, INTP4, and INTP5 are applied when not masked.

2. Only unmasked interrupt request

3. When the watch clock is operating

Remark

NMI is valid only for an external input. The watchdog timer cannot be used for the release of standby

(STOP, HALT, or IDLE mode).

STOP

(standby)

IDLE

(standby)

Request for masked interrupt

HALT

(standby)

INTW

Notes 1, 3

NMI, INTP4, INTP5 input

Note 1

Set STOP

RESET input

Set IDLE

RESET input

INTW

Notes 1, 3

NMI, INTP4, INTP5 input

Note 1

Oscillation settling

time elapses

Wait for

oscillation

settling

Program

operation

Macro service request

End of one operation

End of macro service

Macro

service

Set HALT

RESET input

Interrupt request

Note 2

Macro service request

End of one operation

PD784907, 784908

Data Sheet U11680EJ2V0DS00

12. RESET FUNCTION

When a low-level signal is input to the RESET pin, the internal hardware becomes initialize status (reset status).

When the RESET input makes a low-to-high transition, the following data is loaded into the program counter (PC):

· Low-order 8 bits of the PC:

Contents of address 0000H

· Intermediate 8 bits of the PC: Contents of address 0001H

· High-order 4 bits of the PC:

The PC contents are used as a branch destination address, and program execution starts from that address.

Therefore, a reset start can be performed from an arbitrary address.

The contents of each register can be set by software, as necessary.

The RESET input circuit incorporates a noise eliminator to prevent malfunctions caused by noise. This noise

eliminator is an analog delay sampling circuit.

Figure 12-1. Accepting Reset

For power-on reset, the RESET signal must be held active until the oscillation stabilization time (approximately 40

ms) has elapsed.

Figure 12-2. Power-On Reset

RESET
(input)

Delay

Initialize PC

Execute instruction
of reset start address

Internal reset signal

Start reset

End reset

Oscillation stabilization time

Delay

Initialize PC

Execute instruction of
reset start address

RESET

(input)

Internal reset signal

End reset

PD784907, 784908

Data Sheet U11680EJ2V0DS00

13. REGULATOR

The

PD784908 incorporates a regulator (a circuit which enables low-voltage operation) to reduce the current

consumption of the device. To enable or disable the operation of this regulator, specify the input level of the REGOFF

pin. To disable the operation of the regulator, input a high level signal to the REGOFF pin. To enable operation, input

a low level signal to the REGOFF pin.

When the regulator is turned on, the CPU enters low-power mode. It is recommended to operate this product using

this regulator.

To stabilize the regulator output voltage, connect a capacitor (of about 1

F) to the REGC pin (stabilizing capacitor

connection pin).

When the regulator is stopped, apply the same level as V

to the REGC pin. Figure 13-1 is a block diagram of

the regulator's peripheral circuits.

Figure 13-1. Regulator Peripheral Circuits

Processing for the REGC pin

When the regulator is operating

Connect a capacitor to stabilize the regulator.

When the regulator is stopped

Supply the power supply voltage.

REGOFF

STBC.7

REGC

1 F

Low level: Regulator is turned on.
High level: Regulator is turned off.

Regulator

Internal power supply voltage
(Supplies to the CPU and
peripheral circuits.)

Stops oscillation.

PD784907, 784908

Data Sheet U11680EJ2V0DS00

14. INSTRUCTION SET

(1) 8-bit instructions (The instructions in parentheses are combinations realized by describing A as r)

MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,

ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC, CMPMC,

MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC, CHKL, CHKLA

Table 14-1. Instruction List by 8-Bit Addressing

2nd operand

#byte

saddr

sfr

!addr16

mem

[WHL+]

None

Note 2

saddr'

!!addr24

[saddrp]

PSWL

[WHL]

1st operand

[%saddrg]

PSWH

(MOV)

MOV

(MOV)

Note 6

MOV

(MOV)

MOV

(MOV)

ADD

Note 1

(XCH)

XCH

(XCH)

Note 6

(XCH)

XCH

(XCH)

(ADD)

Note 1

(ADD)

Note 1

(ADD)

Notes 1, 6

(ADD)

Note 1

ADD

Note 1

ADD

Note 1

(ADD)

Note 1

MOV

(MOV)

MOV

ROR

Note 3

MULU

ADD

Note 1

(XCH)

XCH

DIVUW

(ADD)

Note 1

ADD

Note 1

ADD

Note 1

ADD

Note 1

INC

DEC

saddr

MOV

(MOV)

Note 6

MOV

INC

ADD

Note 1

(ADD)

Note 1

ADD

Note 1

XCH

DEC

ADD

Note 1

DBNZ

sfr

MOV

PUSH

ADD

Note 1

(ADD)

Note 1

ADD

Note 1

POP

CHKL

CHKLA

!addr16

MOV

(MOV)

MOV

!!addr24

ADD

Note 1

mem

MOV

[saddrp]

ADD

Note 1

[%saddrg]

mem3

ROR4

ROL4

MOV

PSWL

PSWH

B, C

DBNZ

STBC, WDM

MOV

[TDE+]

(MOV)

MOVBK

Note 5

[TDE]

(ADD)

Note 1

MOVM

Note 4

Notes 1. ADDC, SUB, SUBC, AND, OR, XOR, and CMP are the same as ADD.

2. There is no second operand, or the second operand is not an operand address.

3. ROL, RORC, ROLC, SHR, and SHL are the same as ROR.

4. XCHM, CMPME, CMPMNE, CMPMNC, and CMPMC are the same as MOVM.

5. XCHBK, CMPBKE, CMPBKNE, CMPBKNC, and CMPBKC are the same as MOVBK.

6. When saddr is saddr2 with this combination, an instruction with a short code exists.

PD784907, 784908

Data Sheet U11680EJ2V0DS00

(2) 16-bit instructions (The instructions in parentheses are combinations realized by describing AX as rp)

MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP,

ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW

Table 14-2. Instruction List by 16-Bit Addressing

2nd operand

#word

saddrp

sfrp

!addr16

mem

[WHL+]

byte

None

Note 2

rp'

saddrp'

!!addr24

[saddrp]

1st operand

[%saddrg]

(MOVW)

Note 3

MOVW

(MOVW)

MOVW

(MOVW)

ADDW

Note 1

(XCHW)

Note 3

(XCHW)

XCHW

(XCHW)

(ADD)

Note 1

(ADDW)

Note 1

(ADDW)

Notes 1,3

(ADDW)

Note 1

MOVW

(MOVW)

MOVW

SHRW

MULW

Note 4

ADDW

Note 1

(XCHW)

XCHW

SHLW

INCW

(ADDW)

Note 1

ADDW

Note 1

ADDW

Note 1

ADDW

Note 1

DECW

saddrp

MOVW

(MOVW)

Note 3

MOVW

INCW

ADDW

Note 1

(ADDW)

Note 1

ADDW

Note 1

XCHW

DECW

ADDW

Note 1

sfrp

MOVW

PUSH

ADDW

Note 1

(ADDW)

Note 1

ADDW

Note 1

POP

!addr16

MOVW

(MOVW)

MOVW

MOVTBLW

!!addr24

mem

MOVW

[saddrp]

[%saddrg]

PSW

PUSH

POP

ADDWG

SUBWG

post

PUSH

POP

PUSHU

POPU

[TDE+]

(MOVW)

SACW

byte

MACW

MACSW

Notes 1. SUBW and CMPW are the same as ADDW.

2. There is no second operand, or the second operand is not an operand address.

3. When saddrp is saddrp2 with this combination, an instruction with a short code exists.

4. MULUW and DIVUX are the same as MULW.

PD784907, 784908

Data Sheet U11680EJ2V0DS00

15. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (T

= 25

Parameter

Symbol

Conditions

Ratings

Unit

Supply voltage

0.3 to +6.5

0.3 to V

+ 0.3

0.3 to +0.3

Input voltage

0.3 to V

+ 0.3

Analog input voltage

0.3 to AV

REF1

+ 0.3

Output voltage

0.3 to V

+ 0.3

Output current, low

Per pin

Total of P00 to P07, P30 to

P37, P54 to P57, P60 to P67,

and P100 to P107 pins

Total of P10 to P17, P40 to

P47, P50 to P53, P70 to P77,

P90 to P97, PWM0, PWM1,

and TX pins

Output current, high

Per pin

Total of P00 to P07, P30 to

P37, P54 to P57, P60 to P67,

and P100 to P107 pins

Total of P10 to P17, P40 to

P47, P50 to P53, P70 to P77,

P90 to P97, PWM0, PWM1,

and TX pins

A/D converter reference input

REF1

0.3 to V

+ 0.3

voltage

Operating ambient temperature

40 to +85

Storage temperature

stg

65 to +150

Caution

Product quality may suffer if the absolute maximum rating is exceeded even momentarily for

any parameter. That is, the absolute maximum ratings are rated values at which the product

is on the verge of suffering physical damage, and therefore the product must be used under

conditions that ensure that the absolute maximum ratings are not exceeded.

Remark

Unless otherwise specified, the characteristics of a alternate-function pin are the same as those of a port

pin.

PD784907, 784908

Data Sheet U11680EJ2V0DS00

Main Oscillator Characteristics (T

= 40 to +85

C, V

= 3.5 to 5.5 V, V

= 0 V)

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

Oscillator frequency

Ceramic resonator or crystal resonator

12.58

MHz

Caution

When using the clock generator, wire to avoid adverse influence from wiring capacitance.

Keep the wiring length as short as possible.

Do not cross the wiring with other signal lines.

Do not route the wiring near a signal line through which a high fluctuating current flows.

Make the ground point of the oscillator capacitor the same potential as V

SS1

. Do not ground

the capacitor to a ground pattern in which a high current flows.

Do not fetch signals from the oscillator.

Remark

Connect a 12.582912 MHz or 6.291456 MHz oscillator to operate the internal clock timer with the main

clock.

Clock Oscillator Characteristics (T

= 40 to +85

C, V

= 3.5 to 5.5 V, V

= 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Oscillator frequency

Ceramic resonator or crystal resonator

32.768

kHz

Oscillation stabilization

SXT

= 4.5 to 5.5 V

1.2

time

Oscillation hold voltage

DDXT

3.5

5.5

Watch timer operating

DDW

3.5

5.5

voltage

PD784907, 784908

Data Sheet U11680EJ2V0DS00

DC Characteristics (T

= 40 to +85

C, V

= AV

= 3.5 to 5.5 V, V

= AV

= 0 V) (1/2)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Input voltage, low

Note 5

IL1

For pins other than Notes 1 and 2

0.3

0.3V

IL2

For pins described in Note 1

0.3

0.2V

IL3

= 4.5 to 5.5 V

0.3

+0.8

For pins described in Note 2

Input voltage, high

IH1

For pins other than Notes 1 and 2

0.7V

+ 0.3

IH2

For pins described in Note 1

0.8V

+ 0.3

IH3

= 4.5 to 5.5 V

2.2

+ 0.3

For pins described in Note 2

Output voltage, low

OL1

= 20

0.1

= 100

0.2

= 2 mA

0.4

OL2

= 8 mA

1.0

For pins described in Note 4

= 4.5 to 5.5 V

Output voltage, high

OH1

= 20

0.1

= 100

0.2

= 2 mA

0.4

OH2

= 4.5 to 5.5 V

1.0

= 5 mA

For pins described in Note 3

Notes 1. X1, X2, RESET, P12/ASCK2/SCK2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3,

P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, P32/SCK0, P33/SO0, P105/SCK3, P106/SI3,

P107/SO3, XT1, XT2

2. P40/AD0 to P47/AD7, P50/A8 to P57/A15, P60/A16 to P67/REFRQ/HLDAK, P00 to P07

3. P00 to P07

4. P10 to P17, P40/AD0 to P47/AD7, P50/A8 to P57/A15

5. Other than pull-up resistors

PD784907, 784908

Data Sheet U11680EJ2V0DS00

DC Characteristics (T

= 40 to +85

C, V

= AV

= 3.5 to 5.5 V, V

= AV

= 0 V) (2/2)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Input leakage current

LI1

0 V

For pins other than

X1 and XT1

LI2

X1 and XT1

Output leakage current

0 V

VDD supply current

Note

DD1

Operation mode

= 12.58 MHz

= 4.0 to 5.5 V

= 6.29 MHz

= 3.5 to 5.5 V

DD2

HALT mode

= 12.58 MHz

2.0

4.0

= 4.0 to 5.5 V

CLK

= f

(STBC = B1H)

Peripheral operation

stops.

= 6.29 MHz

1.2

2.4

= 3.5 to 5.5 V

CLK

= f

(STBC = 31H)

Peripheral operation

stops.

DD3

IDLE mode

= 12.58 MHz

0.6

1.2

= 4.0 to 5.5 V

= 6.29 MHz

0.3

0.6

= 3.5 to 5.5 V

Pull-up resistor

= 0 V

X1 and XT1

Note These values are valid when the internal regulator is ON (REGOFF pin = L level). They do not include the

and AV

REF1

currents.

PD784907, 784908

Data Sheet U11680EJ2V0DS00

AC Characteristics (T

= 40 to +85

C, V

= AV

= 3.5 to 5.5 V, AV

= V

= 0 V)

(1) Read/write operation

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

Address setup time (to ASTB

)

SAST

= 5.0 V

(0.5 + a)T 11

ASTB high-level width

WSTH

= 5.0 V

(0.5 + a)T 17

Address hold time (from ASTB

)

HSTLA

= 5.0 V

0.5T 19

Address hold time (from RD

)

HRA

= 5.0 V

0.5T 14

Delay from address to RD

DAR

= 5.0 V

(1 + a)T 5

Address float time (from RD

)

FRA

Data input time from address

DAID

= 5.0 V

(2.5 + a + n)T 37

400

Data input time from ASTB

DSTID

= 5.0 V

(2 + n)T 35

283

Data input time from RD

DRID

= 5.0 V

(1.5 + n)T 40

238

Delay from ASTB

to RD

DSTR

= 5.0 V

0.5T 9

Data hold time (from RD

)

HRID

Address active time from RD

DRA

= 5.0 V

0.5T 2

Delay from RD

to ASTB

DRST

= 5.0 V

0.5T 9

RD low-level width

WRL

= 5.0 V

(1.5 + n)T 25

Delay from address

to WR

DAW

= 5.0 V

(1 + a)T 5

Address hold time (from WR

)

HWA

= 5.0 V

0.5T 14

Delay from ASTB

to data output

DSTOD

= 5.0 V

0.5T + 15

Delay from WR

to data output

DWOD

Delay from ASTB

to WR

DSTW

= 5.0 V

0.5T 9

Data setup time (to WR

)

SODWR

= 5.0 V

(1.5 + n)T 20

Data hold time (from WR

)

HWOD

= 5.0 V

0.5T 14

Delay from WR

to ASTB

DWST

= 5.0 V

0.5T 9

WR low-level width

WWL

= 5.0 V

(1.5 + n)T 25

Remark

CYK

(system clock cycle time) V

= 5.0 V T = 79 ns (MIN.)

1 during address wait, otherwise, 0

number of wait states (n

PD784907, 784908

Data Sheet U11680EJ2V0DS00

(2) External wait timing

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

WAIT

input time from address

DAWT

= 5.0 V

(2 + a)T 40

198

WAIT

input time from ASTB

DSTWT

= 5.0 V

1.5T 40

WAIT hold time from ASTB

HSTWT

= 5.0 V

(0.5 + n)T + 5

124

Delay from ASTB

to WAIT

DSTWTH

= 5.0 V

(1.5 + n)T 40

238

WAIT

input time from RD

DRWTL

= 5.0 V

T 40

WAIT hold time from RD

HRWT

= 5.0 V

nT + 5

Delay from RD

to WAIT

DRWTH

= 5.0 V

(1 + n)T 40

198

Data input time from WAIT

DWTID

= 5.0 V

0.5T 5

Delay from WAIT

to RD

DWTR

= 5.0 V

0.5T

Delay from WAIT

to WR

DWTW

= 5.0 V

0.5T

WAIT

input time from WR

DWWTL

= 5.0 V

T 40

WAIT hold time from WR

HWWT

= 5.0 V

nT + 5

Delay from WR

to WAIT

DWWTH

= 5.0 V

(1 + n)T 40

198

Remark

CYK

(system clock cycle time) V

= 5.0 V T = 79 ns (MIN.)

1 during address wait, otherwise, 0

number of wait states (n

PD784907, 784908

Data Sheet U11680EJ2V0DS00

(3) Bus hold timing

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

Delay from HLDRQ

to float

FQHC

= 5.0 V

(2 + 4 + a + n)T + 50

765

Delay from HLDRQ

to HLDAK

DHQHHAH

= 5.0 V

(3 + 4 + a + n)T + 30

825

Delay from float to HLDAK

DCFHA

= 5.0 V

T + 30

109

Delay from HLDRQ

to HLDAK

DHQLHAL

= 5.0 V

2T + 40

199

Delay from HLDRQ

to active

DHAC

= 5.0 V

T 20

Remark T:

CYK

(system clock cycle time) V

= 5.0 V T = 79 ns (MIN.)

1 during address wait, otherwise, 0

number of wait states (n

(4) Refresh timing

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

Random read/write cycle time

= 5.0 V

238

REFRQ low-level pulse width

WRFQL

= 5.0 V

1.5T 25

Delay from ASTB

to REFRQ

DSTRFQ

= 5.0 V

0.5T 9

Delay from RD

to REFRQ

DRRFQ

= 5.0 V

1.5T 9

110

Delay from WR

to REFRQ

DWRFQ

= 5.0 V

1.5T 9

110

Delay from REFRQ

to ASTB

DRFQST

= 5.0 V

0.5T 9

REFRQ high-level pulse width

WRFQH

= 5.0 V

1.5T 25

Remark

CYK

(system clock cycle time) V

= 5.0 V T = 79 ns (MIN.)

PD784907, 784908

Data Sheet U11680EJ2V0DS00

Serial Operation (T

= 40 to +85

C, V

= 3.5 to 5.5 V, AV

= V

= 0 V)

(1) CSI, CSI3

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

Serial clock cycle time

CYSK0

Input

CLK

= f

8/f

(SCK0, SCK3)

Except f

CLK

= f

4/f

CLK

Output Except f

CLK

= f

8/f

CLK

= f

16/f

Serial clock low-level width

WSKL0

Input

CLK

= f

4/f

(SCK0, SCK3)

Except f

CLK

= f

2/f

CLK

Output Except f

CLK

= f

4/f

CLK

= f

8/f

Serial clock high-level width

WSKH0

Input

CLK

= f

4/f

(SCK0, SCK3)

Except f

CLK

= f

2/f

CLK

Output Except f

CLK

= f

4/f

CLK

= f

8/f

SI0, SI3 setup time

SSSK0

(to SCK0, SCK3

)

SI0, SI3 hold time

HSSK0

External clock

1/f

CLK

+ 80

(from SCK0, SCK3

)

Internal clock

SO0, SO3 output delay time

DSBSK1

CMOS push-pull output

External clock

1/f

CLK

+ 150

(from SCK0, SCK3

)

Internal clock

150

DSBSK2

Open-drain output

External clock

1/f

CLK

+ 400

= 1 k

Internal clock

400

SO0, SO3 output hold time

HSBSK

When data is transferred

0.5t

CYSK0

(from SCK0, SCK3

)

Remarks 1. The values in this table are those when f

= 12.58 MHz, C

= 100 pF.

2. f

CLK

: system clock frequency (selectable from f

, f

/2, f

/4, and f

/8 by the standby control

3. f

: oscillation frequency (f

= 12.58 MHz or f

= 6.29 MHz)

PD784907, 784908

Data Sheet U11680EJ2V0DS00

(2) IOE1, IOE2 (T

= 40 to +85

C, V

= AV

= 3.5 to 5.5 V, AV

= V

= 0 V)

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

Serial clock cycle time

CYSK1

Input

= 4.0 to 5.5 V

640

(SCK1, SCK2)

1,280

Output Internal, divided by 8

Serial clock low-level width

WSKL1

Input

= 4.0 to 5.5 V

280

(SCK1, SCK2)

600

Output Internal, divided by 8

0.5T 40

Serial clock high-level width

WSKH1

Input

= 4.0 to 5.5 V

280

(SCK1, SCK2)

600

Output Internal, divided by 8

0.5T 40

SI1, SI2 setup time

SSSK1

(to SCK1, SCK2

)

SI1, SI2 hold time

HSSK1

(from SCK1, SCK2

)

SO1, SO2 output delay time

DSOSK

(from SCK1, SCK2

)

SO1, SO2 output hold time

HSOSK

When data is transferred

0.5t

CYSK1

(from SCK1, SCK2

)

Remarks 1. The values in this table are those when C

= 100 pF.

2. T: serial clock cycle set by software. The minimum value is 8/f

(3) UART, UART2 (T

= 40 to +85

C, V

= AV

= 3.5 to 5.5 V, AV

= V

= 0 V)

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

ASCK clock input cycle time

CYASK

= 4.5 to 5.5 V

160

320

ASCK clock low-level width

WASKL

= 4.5 to 5.5 V

120

ASCK clock high-level width

WASKH

= 4.5 to 5.5 V

120

PD784907, 784908

Data Sheet U11680EJ2V0DS00

Clock Output Operation (T

= 40 to +85

C, V

= AV

= 3.5 to 5.5 V, AV

= V

= 0 V)

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

CLKOUT cycle time

CYCL

32,000

CLKOUT low-level width

CLL

= 4.0 to 5.5 V, 0.5T 10

0.5T 20

CLKOUT high-levell width

CLH

= 4.0 to 5.5 V, 0.5T 10

0.5T 20

CLKOUT rising time

CLR

= 4.0 to 5.5 V

= 3.5 to 4.0 V

0.3

CLKOUT falling time

CLF

= 4.0 to 5.5 V

= 3.5 to 4.0 V

0.3

Remark n:

Dividing ratio set by software in the CPU (n = 1, 2, 4, 8, and 16)

CYK

(system clock cycle time)

Other Operations (T

= 40 to +85

C, V

= AV

= 3.5 to 5.5 V, AV

= V

= 0 V)

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

NMI low-level width

WNIL

NMI high-level width

WNIH

INTP0 low-level width

WIT0L

CYSMP

INTP0 high-level width

WIT0H

CYSMP

INTP1 to INTP3 and CI

WIT1L

CYCPU

low-level width

INTP1 to INTP3 and CI

WIT1H

CYCPU

high-level width

INTP4 and INTP5 low-level width

WIT2L

INTP4 and INTP5 high-level width

WIT2H

RESET low-level width

Note

WRSL

RESET high-level width

WRSH

Note When the power is ON, secure the oscillation stabilization wait time with the RESET low-level width.

Remark t

CYSMP

: sampling clock set by software

CYCPU

: CPU operation clock set by software in the CPU

PD784907, 784908

Data Sheet U11680EJ2V0DS00

A/D Converter Characteristics (T

= 40 to +85

C, V

= AV

REF1

= 3.5 to 5.5 V, V

= AV

= 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Resolution

bit

Total error

Note

IEAD = 00H

0.6

FR = 1

1.5

IEAD = 01H

= 4.5 to 5.5 V

2.2

Quantization error

1/2

LSB

Conversion time

CONV

FR = 1 120/f

CLK

9.5

480

FR = 0 240/f

CLK

19.1

960

Sampling time

SAMP

FR = 1 18/f

CLK

1.4

FR = 0 36/f

CLK

2.9

144

Analog input impedance

1,000

REF1

impedance

REF1

power supply current

DD1

CS = 1

2.0

5.0

DD2

CS = 0, STOP mode

1.0

Note Quantization error is not included. This parameter is indicated as the ratio to the full-scale value.

Caution

To execute the conversion by the A/D converter set port 7, multiplexed with the A/D input lines,

to output mode to prevent data from being inverted.

Remark

CLK

: system clock frequency (selectable from f

, f

/2, f

/4, and f

/8 by the standby control register

(STBC))

IEBus Controller Characteristics (T

= 40 to +85

C, V

= AV

REF1

= 4.5 to 5.5 V, AV

= V

= 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

IEBus standard

Transfer speed: mode 1

6.20

6.29

6.39

MHz

frequency

Note 1

Driver delay time (from

DTX

= 50 pF

Note 3

1.5

TX output to bus line)

Note 2

Receiver delay time (from t

DRX

0.7

bus line to RX input)

Note 2

Transmission delay on

DBUS

0.85

bus

Note 2

Notes 1. The value conforms to the IEBus standard. The IEBus controller is operable within the range of the

oscillator frequency of oscillator characteristics.

2. IEBus system clock: The value is measured when f

= 6.29 MHz.

3. C is the load capacitance of TX output line.

PD784907, 784908

Data Sheet U11680EJ2V0DS00

Data Retention Characteristics (T

= 40 to +85

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Data retention voltage

DDDR

STOP mode

2.5

5.5

Data retention current

DDDR

STOP mode

DDDR

= 2.5 V,

REF

= 0 V

Note 1

DDDR

= 3.5 to 5.5 V,

REF

= 0 V

Note 1

rising time

RVD

200

falling time

FVD

200

hold time

HVD

0.6

(from STOP mode setting)

STOP clear signal

DREL

input time

Oscillation settling time

WAIT

Crystal resonator

Ceramic resonator

0.1V

DDDR

Input low voltage

Specific pins

Note 2

DDDR

Input high voltage

0.9V

DDDR

Notes 1. Valid when input voltages to the pins described in Note 2 satisfy V

or V

in the above table.

2. RESET, P12/ASCK2/SCK2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3,

P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, P32/SCK0, P33/SO0, P105/SCK3, P106/SI3, and

P107/SO3 pins

AC Timing Test Points

0.8 V

or 2.2 V

0.8 V

or 2.2 V

0.8 V

Test points

1 V

0.45 V

PD784907, 784908

Data Sheet U11680EJ2V0DS00

Soldering Method

Soldering Conditions

Recommended Condition

Symbol

Infrared reflow

Package peak temperature: 235

IR35-00-3

Time: 30 seconds max. (210

C or higher)

Count: three times or less

VPS

Package peak temperature: 215

VP15-00-3

Time: 40 seconds or max. (200

C or higher)

Count: three times or less

Wave soldering

Solder bath temperature: 260

C max.

WS60-00-1

Time: 10 seconds max.

Count : 1

Preheating temperature: 120

C max. (package surface temperature)

Partial heating method

Pin temperature: 300

Time: 3 seconds max. (per pin row)

17. RECOMMENDED SOLDERING CONDITIONS

The

PD784908 should be soldered under the following recommended conditions.

For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting

Technology Manual (C10535E).

For soldering methods and conditions other than those recommended below, contact your NEC sales represen-

tative.

Table 17-1. Soldering Conditions for Surface Mount Type

PD784907GF-

×××

-3BA: 100-pin plastic QFP (14

20 mm)

PD784908GF-

×××

-3BA: 100-pin plastic QFP (14

20 mm)

Caution

Do not use different soldering methods together (except for partial heating).

PD784907, 784908

Data Sheet U11680EJ2V0DS00

APPENDIX A DEVELOPMENT TOOLS

The following development tools are available for system development using the

PD784908.

Also refer to (5) Cautions on using development tools.

(1) Language processing software

RA78K4

Assembler package common to 78K/IV Series

CC78K4

C compiler package common to 78K/IV Series

DF784908

Device file for

PD784908 Subseries

CC78K4-L

C compiler library source file common to 78K/IV Series

(2) PROM write tools

PG-1500

PROM programmer

PA-78P4908GF

Programmer adapter, connects to PG-1500

PG-1500 controller

Control program for PG-1500

(3) Debugging tools

· When using the in-circuit emulator IE-78K4-NS

IE-78K4-NS

In-circuit emulator common to 78K/IV Series

IE-70000-MC-PS-B

Power supply unit for IE-78K4-NS

IE-70000-98-IF-C

Interface adapter when a PC-9800 Series computer (except notebook type)

is used as the host machine (C bus supported)

IE-70000-CD-IF-A

PC card and interface cable when a notebook type is used as the

host machine (PCMCIA socket supported)

IE-70000-PC-IF-C

Interface adapter when an IBM PC/AT

or compatible is used as the host

machine (ISA bus supported)

IE-70000-PCI-IF

Adapter when a PC that incorporates a PCI bus is used as the host machine

IE-784908-NS-EM1

Emulation board to emulate

PD784908 Subseries

NP-100GF

Note

Emulation probe for 100-pin plastic QFP (GF-3BA type)

EV-9200GF-100

Socket to be mounted on target system board made for 100-pin plastic QFP

(GF-3BA type). Used in LCC mode.

ID78K4-NS

Integrated debugger for IE-78K4-NS

SM78K4

System simulator common to 78K/IV Series

DF784908

Device file for

PD784908 Subseries

Note Under development

PD784907, 784908

Data Sheet U11680EJ2V0DS00

· When using the in-circuit emulator IE-784000-R

IE-784000-R

In-circuit emulator common to 78K/IV Series

IE-70000-98-IF-C

Interface adapter when a PC-9800 Series computer (except notebook type)

is used as the host machine (C bus supported)

IE-70000-PC-IF-C

Interface adapter when an IBM PC/AT or compatible is used as the host

machine (ISA bus supported)

IE-70000-PCI-IF

Adapter when a PC that incorporates a PCI bus is used as the host machine

IE-78000-R-SV3

Interface adapter and cable when the EWS is used as the host machine

IE-784908-NS-EM1

Emulation board to emulate

PD784908 Subseries

IE-784908-R-EM1

IE-784000-R-EM

Emulation board common to 78K/IV Series

IE-78K4-R-EX2

Conversion board for emulation probes required to use the IE-784908-NS-

EM1 on the IE-784000-R. The board is not needed when the conventional

product IE-784908-R-EM1 is used.

EP-78064-GF-R

Emulation probe for 100-pin plastic QFP (GF-3BA type)

EV-9200GF-100

Socket to be mounted on target system board made for 100-pin plastic QFP

(GF-3BA type)

ID78K4

Integrated debugger for IE-784000-R

SM78K4

System simulator common to 78K/IV Series

DF784908

Device file for

PD784908 Subseries

(4) Real-time OS

RX78K/IV

Real-time OS for 78K/IV Series

MX78K4

OS for 78K/IV Series

PD784907, 784908

Data Sheet U11680EJ2V0DS00

APPENDIX B RELATED DOCUMENTS

Documents related to devices

Document Name

Document No.

Japanese

English

PD784907, 784908 Data Sheet

U11680J

This manual

PD78P4908 Data Sheet

U11681J

U11681E

PD784908 Subseries User's Manual Hardware

U11787J

U11787E

PD784908 Subseries Special Function Register Table

U11589J

78K/IV Series User's Manual Instructions

U10905J

U10905E

78K/IV Series Instruction Table

U10594J

78K/IV Series Instruction Set

U10595J

78K/IV Series Application Note Software Basics

U10095J

U10095E

Documents related to development tools (User's Manual)

Document Name

Document No.

Japanese

English

RA78K4 Assembler Package

Language

U11162J

U11162E

Operation

U11334J

U11334E

RA78K4 Structured Assembler Preprocessor

U11743J

U11743E

CC78K4 C Compiler

Language

U11571J

U11571E

Operation

U11572J

U11572E

PG-1500 PROM Programmer

U11940J

U11940E

PG-1500 Controller PC-9800 Series (MS-DOS

) Based

EEU-704

EEU-1291

PG-1500 Controller IBM PC Series (PC DOS

) Based

EEU-5008

U10540E

IE-78K4-NS

U13356J

U13356E

IE-784000-R

U12903J

U12903E

IE-784908-R-EM1

U11876J

IE-784908-NS-EM1

U13743J

Under preparation

EP-78064

EEU-934

EEU-1469

SM78K4 System Simulator Windows Based

Reference

U10093J

U10093E

SM78K Series System Simulator

External Part User Open

U10092J

U10092E

Interface Specifications

ID78K4-NS Integrated Debugger PC Based

Reference

U12796J

U12796E

ID78K4 Integrated Debugger Windows Based

Reference

U10440J

U10440E

ID78K4 Integrated Debugger HP-UX, SunOS, NEWS-OS Based

Reference

U11960J

U11960E

Caution

The above documents may be revised without notice. Use the latest versions when you design

application systems.

PD784907, 784908

Data Sheet U11680EJ2V0DS00

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction of

the gate oxide and ultimately degrade the device operation. Steps must be taken

to stop generation of static electricity as much as possible, and quickly dissipate

it once, when it has occurred. Environmental control must be adequate. When

it is dry, humidifier should be used. It is recommended to avoid using insulators

that easily build static electricity. Semiconductor devices must be stored and

transported in an anti-static container, static shielding bag or conductive

material. All test and measurement tools including work bench and floor should

be grounded. The operator should be grounded using wrist strap. Semiconductor

devices must not be touched with bare hands. Similar precautions need to be

taken for PW boards with semiconductor devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input level

may be generated due to noise, etc., hence causing malfunction. CMOS device

behave differently than Bipolar or NMOS devices. Input levels of CMOS devices

must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V

or GND with a resistor, if it is considered to have

a possibility of being an output pin. All handling related to the unused pins must

be judged device by device and related specifications governing the devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production

process of MOS does not define the initial operation status of the device.

Immediately after the power source is turned ON, the devices with reset function

have not yet been initialized. Hence, power-on does not guarantee out-pin

levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after

power-on for devices having reset function.

PD784907, 784908

Data Sheet U11680EJ2V0DS00

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

Device availability

Ordering information

Product release schedule

Availability of related technical literature

Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490

NEC Electronics (UK) Ltd.

Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290

NEC Electronics Italiana s.r.l.

Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99

NEC Electronics (Germany) GmbH

Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580

NEC Electronics (France) S.A.

Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99

NEC Electronics (France) S.A.

Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860

NEC Electronics (Germany) GmbH

Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130
Tel: 65-253-8311
Fax: 65-250-3583

NEC Electronics Taiwan Ltd.

Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951

NEC do Brasil S.A.

Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829

J98. 11

PD784907, 784908

Data Sheet U11680EJ2V0DS00

The related documents in this publication may include preliminary version. However, what preliminary versions

are not marked as such.

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.

No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on
a customer designated "quality assurance program" for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.

M4 96. 5

FIP, IEBus, and EEPROM are trademarks of NEC Corporation.

MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the

United States and/or other countries.

PC/AT and PC DOS are trademarks of International Business Machines Corporation.

HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.

SPARCstation is a trademark of SPARC International, Inc.

Solaris and SunOS are trademarks of Sun Microsystems, Inc.

NEWS and NEWS-OS are trademarks of Sony Corporation.

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Document Outline

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